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MCIMX6DP4AVT2AB bảng dữ liệu(PDF) 86 Page - NXP Semiconductors |
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MCIMX6DP4AVT2AB bảng dữ liệu(HTML) 86 Page - NXP Semiconductors |
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86 / 160 page ![]() i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018 86 NXP Semiconductors Electrical Characteristics Figure 46. RGMII Receive Signal Timing Diagram Original Figure 47. RGMII Receive Signal Timing Diagram with Internal Delay 4.12.6 Flexible Controller Area Network (FlexCAN) AC Electrical Specifications The Flexible Controller Area Network (FlexCAN) module is a communication controller implementing the CAN protocol according to the CAN 2.0B protocol specification.The processor has two CAN modules available for systems design. Tx and Rx ports for both modules are multiplexed with other I/O pins. See the IOMUXC chapter of the i.MX 6DualPlus/6QuadPlus reference manual (IMX6DQPRM) to see which pins expose Tx and Rx pins; these ports are named FLEXCAN_TX and FLEXCAN_RX, respectively. 4.12.7 HDMI Module Timing Parameters 4.12.7.1 Latencies and Timing Information Power-up time (time between TX_PWRON assertion and TX_READY assertion) for the HDMI 3D Tx PHY while operating with the slowest input reference clock supported (13.5 MHz) is 3.35 ms. |
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