SL3S1205FUD2SLASHHAP datasheet(14/38 Pages) NXP

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NXP Semiconductors

SL3S1205_15

UCODE 8/8m

Polyimide spacer

10 μm ± 2 μm

Au pads

Pad material

> 99.9 % pure Au

Pad hardness

35 – 80 HV 0.005

Pad shear strength

> 70 MPa

Pad height

3 μm

Pad height uniformity

– within a die

max. 2 μm

– within a wafer

max. 4 μm

Pad flatness

max. 3 μm

Pad size

– RF1, RF2 (max. details see wafer layout)

151.5 μm × 278 μm

– TP1, TP2 (max. details see wafer layout)

134.2 μm × 100 μm

Pad size variation

± 5 μm

Table 5. 12 inch specification with Large Pads, plasma dicing ...continued

8.1.3 Fail die identification

No ink dots are applied to the wafer.

Electronic wafer mapping (SECS II format) covers the electrical test results and

additionally the results of mechanical/visual inspection.

See "Data sheet - Delivery type description – General specification for 8" wafer on UV-

tape with electronic fail die marking, BU-S&C document number: 1093**"

See "Data sheet - Delivery type description – General specification for 12" wafer on UV-

tape with electronic fail die marking, BU-S&C document number: 1862**"

8.1.4 Map file distribution

See "Data sheet - Delivery type description – General specification for 8" wafer on UV-

tape with electronic fail die marking, BU-S&C document number: 1093**"

See "Data sheet - Delivery type description – General specification for 12" wafer on UV-

tape with electronic fail die marking, BU-S&C document number: 1862**"

SL3S1205_15

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.5 — 1 April 2021

COMPANY PUBLIC

398435

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