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MTC20455 bảng dữ liệu(PDF) 19 Page - STMicroelectronics

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MTC20455
Utopia Level 2 Signals
The physical layer chip sends cell data towards the ATM layer chip. The ATM layer chip polls the status
of the FIFO of the physical layer chip. Refer to Table 6 for a list of interface signals. The cell exchange
proceeds like:
a) The physical layer chip signals the availability of a cell by asserting RxClav when polled by the ATM
chip.
b) The ATM chips selects a physical layer chip, then starts the transfer by asserting notRxEnb.
c) If the physical layer chip has data to send, it puts them on the RxData line the cycle after it sampled
notRxEnb active. It also advances the offset in the cell. If the data transferred is the first byte of a cell,
RxSOC is 1b at the time of the data transfer, 0b otherwise.
d) The ATM chip accepts the data when they are available. If RxSOC was 1b during the transfer, it resets
its internal offset pointer to the value 1, otherwise it advances the offset in the cell.
MTC20455 Utopia Level 2 MPHY Operation
Utopia level 2 MPHY operation can be done by various interface schemes. The MTC20455 supports only
the required mode, this mode is referred to as «operation with 1 TxClav and 1 RxClav.»
PHY Device Identification
The MTC20455 holds 2 PHY layer Utopia ports, one is dedicated to the fast data channel, the other one
to the interleaved data channel. The associated PHY address is specified by the PHY_ADDR_x fields the
Utopia PHY address register. Beware that an incorrect address configuration may lead to bus conflicts.
MTC20136 Transceiver Controller Interface
Table 18. All signals
Figure 12. PCLK Clock frequency
Table 19. Address with respect to ALE
Symbol
Parameter
Min
Typ
Max
Unit
tr, tf
Rise and Fall time (10% - 90%)
3
ns
Ci
Input load
10
pF
Co
Output load
20
pF
Symbol
Parameter
Min
Typ
Max
Unit
f
PCLK clock frequency
8
33
MHz
Symbol
Parameter
Min
Typ
Max
Unit
tr,tf
Rise and Fall time (10% - 90%)
4
ns
Talew
ALE pulse width
12
ns
Tavs
Address valid setup time
7
ns
Tavh
Address valid hold time
8
ns



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