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TBD bảng dữ liệu(PDF) 1 Page - Integrated Circuit Systems |
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TBD bảng dữ liệu(HTML) 1 Page - Integrated Circuit Systems |
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1 / 20 page ![]() 843020AY-01 www.icst.com/products/hiperclocks.html REV. B APRIL 14, 2005 1 Integrated Circuit Systems, Inc. ICS843020-01 FEMTOCLOCKS™ 680MHZ, CRYSTAL-TO- 3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION The ICS843020-01 is a general purpose, dual out- put Crystal-to-3.3V Differential LVPECL High Fre- quency Synthesizer and a member of the FemtoClocks™ family of High Performance Clock Solutions from ICS. The ICS843020-01 is based on ICS’ 3rd generation VCO technology and is capable of sub- 1ps RMS Phase Jitter performance, making it ideal for use in 10 Gigabit Ethernet, 10 Gigabit Fibre Channel, SONET and Serial ATA applications. The ICS843020-01 is a highly flexible programmable synthe- sizer capable of generating output frequencies over a range of 70MHz to 680MHz. The output frequency can be programmed in small step sizes as low as 250 kHz when using a 16MHz crystal, ÷8 input divider, and output divider = ÷8. BLOCK DIAGRAM PIN ASSIGNMENT FEATURES • Dual differential 3.3V LVPECL outputs • Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK • Output frequency range: 70MHz to 680MHz • Crystal input frequency range: 12MHz to 32MHz • VCO range: 560MHz to 680MHz • Parallel or serial interface for programming feedback and output dividers • Input P_DIV under parallel load control • RMS phase jitter at 156.25MHz (1.875MHz to 20MHz): 0.49ps (typical), P_DIV = ÷1 • 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Lead-Free package fully RoHS compliant 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 XTAL_OUT TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR M5 M6 M7 M8 N0 N1 P_DIV VEE 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View ICS843020-01 HiPerClockS™ ICS OSC VCO_SEL XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT P_DIV S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1 VCO PLL FOUT0 nFOUT0 FOUT1 nFOUT1 TEST CONFIGURATION INTERFACE LOGIC ÷ M 0 1 0 1 PHASE DETECTOR MR ÷ 1 ÷ 2 ÷ 4 ÷ 8 0 ÷8 Float ÷1 (default) 1 ÷4 ÷N ÷ P |
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