ICS671-03

3.3 Volt Zero Delay, Low Skew Buffer

MDS 671-03 A

1

Revision 072501

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408) 295-9800 tel • www.icst.com

PRELIMINARY INFORMATION

Block Diagram

Description

Features

The ICS671-03 is a low phase noise, high speed PLL

based, 8 output, low skew zero delay buffer. Based on

ICS’s proprietary low jitter Phase Locked Loop (PLL)

techniques, the device provides eight low skew

outputs at speeds up to 133 MHz at 3.3 V. The

outputs can be generated from the PLL (for zero

delay), or directly from the input (for testing), and can

be set to tri-state mode or to stop at a low level. For

normal operation as a zero delay buffer, any output

clock is tied to the FBIN pin.

ICS manufactures the largest variety of clock

generators and buffers, and is the largest clock

supplier in the world.

• Packaged in 16 pin narrow (150 mil) SOIC

• Clock outputs from 10 to 133 MHz

• Zero input-output delay

• Eight low-skew (<200 ps) outputs

• Device-to-device skew <700 ps

• Low jitter (<200 ps)

• Full CMOS outputs with 25 mA output drive

capability at TTL levels

• 5 V tolerant FBIN and CLKIN pins

• Tri-state mode for board-level testing

• Advanced, low power, sub-micron CMOS process

• 3.3 V operating voltage

• Industrial temperature range of -40 to 85 °C

Clock

Synthesis

PLL

CLKA1

FBIN

CLKA2

S2, S1

2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

Control

Logic

CLKIN

Feedback is shown from CLKB4 for illustration, but may

come from any output.