843004AGI-01

www.icst.com/products/hiperclocks.html

REV. A FEBRUARY 11, 2005

9

Integrated

Circuit

Systems, Inc.

ICS843004I-01

VCC=3.3V

VDD

Zo = 50 Ohm

+

-

18pF

R5

133

RD1

Not Install

To Logic

Input

pins

VCC

Zo = 50 Ohm

RU2

Not Install

3.3V

R9

133

U1

ICS843004-01

VCC

C3

10uF

+

-

R3

133

C7

0.1u

X1

25MHz

Zo = 50 Ohm

R7

133

3.3V

VDD

R6

82.5

VCCA

C4

0.01u

C8

0.1u

VCCO=3.3V

Logic Control Input Examples

C6

0.1u

C2

33pF

C9

0.1u

R2

10

RU1

1K

R4

82.5

Set Logic

Input to

'1'

C1

27pF

To Logic

Input

pins

R10

82.5

Zo = 50 Ohm

R8

82.5

Set Logic

Input to

'0'

VCCO

RD2

1K

Figure 5 shows a schematic example of the ICS843004I-01. An

example of LVEPCL termination is shown in this schematic. Ad-

ditional LVPECL termination approaches are shown in the

LVPECL Termination Application Note. In this example, an 18pF

parallel resonant 25MHz crystal is used. The C1=27pF and

C2=33pF are recommended for frequency accuracy. For differ-

ent board layout, the C1 and C2 may be slightly adjusted for

optimizing frequency accuracy.

ICS843004I-01