843004AGI

www.icst.com/products/hiperclocks.html

REV. A FEBRUARY 11, 2005

10

Integrated

Circuit

Systems, Inc.

ICS843004I

Figure 5 shows a schematic example of the ICS843004I. An

example of LVEPCL termination is shown in this schematic. Ad-

ditional LVPECL termination approaches are shown in the

LVPECL Termination Application Note. In this example, an 18pF

parallel resonant 26.5625MHz crystal is used. The C1=27pF

and C2=33pF are recommended for frequency accuracy. For

different board layout, the C1 and C2 may be slightly adjusted

for optimizing frequency accuracy.

VCC=3.3V

C3

10uF

+

-

VCCO=3.3V

R3

133

To Logic

Input

pins

3.3V

VCC

Zo = 50 Ohm

Set Logic

Input to

'0'

C7

0.1u

3.3V

RD2

1K

VCC

VDD

R10

82.5

R4

82.5

VCCA

Logic Control Input Examples

VDD

C2

33pF

C4

0.01u

+

-

Zo = 50 Ohm

RD1

Not Install

Zo = 50 Ohm

RU2

Not Install

R7

133

R8

82.5

C9

0.1u

C1

27pF

Set Logic

Input to

'1'

R9

133

X1

26.5625MHz

R2

10

18pF

To Logic

Input

pins

Zo = 50 Ohm

VCCO

R6

82.5

C6

0.1u

U1

ICS843004

C8

0.1u

R5

133

RU1

1K