85314BGI-01

www.icst.com/products/hiperclocks.html

REV. E SEPTEMBER 23, 2005

13

Integrated

Circuit

Systems, Inc.

ICS85314I-01

This section provides information on power dissipation and junction temperature for the ICS85314I-01.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS85314I-01 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

If all outputs are loaded, the total power is 5 * 30.2mW = 151mW

Total Power

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

The equation for Tj is as follows: Tj =

θ

Tj = Junction Temperature

θ

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance

θ

moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6A below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.455W * 66.6°C/W = 115°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

θθθθθ

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

114.5°C/W

98.0°C/W

88.0°C/W

Multi-Layer PCB, JEDEC Standard Test Boards

73.2°C/W

66.6°C/W

63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

θθθθθ

JA

FOR

θθθθθ

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

83.2°C/W

65.7°C/W

57.5°C/W

Multi-Layer PCB, JEDEC Standard Test Boards

46.2°C/W

39.7°C/W

36.8°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

θθθθθ

JA

FOR