810001BK-21

www.icst.com/products/hiperclocks.html

REV. A AUGUST 12, 2005

17

Integrated

Circuit

Systems, Inc.

ICS810001-21

PRELIMINARY

The example above will ensure a total pull range of ±113.25

ppm with an APR of ±58.25ppm. Many times, board designers

may select their own crystal based on their application. If the

application requires a tighter APR, a crystal with better pullability

C

(C

(C

C

(C

(C

C

Low

is the effective capacitance due to the low varactor

capacitance, load capacitance and stray capacitance.

C

TPR (Total Pull Range).

C

High

is the effective capacitance due to the high varactor

capacitance, load capacitance and stray capacitance.

C

TPR (Total Pull Range).

Using the tables and figures above, we can now calculate the

TPR and APR of the VCXO using the example crystal

parameters. For the numerical example below there were some

assumptions made. First, the stray capacitance (C

is all the excess capacitance due to board parasitic, is 4pF.

Second, the expected lifetime of the project is 5 years; hence

the inaccuracy due to aging is ±15ppm. Third, though many

boards will not require load tuning capacitors (C

recommended for long-term consistent performance of the

system that two tuning capacitor pads be placed into every

design. Typical values for the load tuning capacitors will range

from 0 to 4pF.

AbsolutePullRange (APR) = TotalPullRange – (FrequencyTolerance + FrequencyStability + Aging)

TPR =

1

2 · C

1

2 · C

()

C

(0 + 4pF + 15.4pF) · (0 + 4pF + 15.4pF)

(0 + 4pF + 15.4pF) + (0 + 4pF + 15.4pF)

= 9.7pF

C

(0 + 4pF + 29.6pF) · (0 + 4pF + 29.6pF)

(0 + 4pF + 29.6pF) + (0 + 4pF + 29.6pF)

= 16.8pF

TPR = ±113.25ppm

APR = 113.25ppm – (20ppm + 20ppm + 15ppm) = ±58.25ppm

TPR =

1

2 · 220 · (1+9.7pF/4pF)

1

2 · 220 · (1+16.8pF/4pF)

()

(C0/C1 ratio) can be used. Also, with the equations above, one

can vary the frequency tolerance, temperature stability, and

aging or shunt capacitance to achieve the required pullability.