PCIMX6D4AVT08AC datasheet(39/162 Pages) NXP

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Electrical Characteristics

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018

NXP Semiconductors

4.6.4.1

LPDDR2 Mode I/O DC Parameters

For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported

DDR3/DDR3L/LPDDR2 Configurations.”

The parameters in Table 23 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

Schmitt trigger VT+ 3, 4

VTH+

—0.5xOVDD

—

Schmitt trigger VT- 3, 4

VTH-

—

0.5xOVDD

Pull-up resistor (22 k

Ω PU)

RPU_22K

Vin=0V

—

212

μA

Pull-up resistor (22 k

Ω PU)

RPU_22K

Vin=OVDD

—

μA

Pull-up resistor (47 k

Ω PU)

RPU_47K

Vin=0V

—

100

μA

Pull-up resistor (47 k

Ω PU)

RPU_47K

Vin=OVDD

—

μA

Pull-up resistor (100 k

Ω PU)

RPU_100K

Vin=0V

—

μA

Pull-up resistor (100 k

Ω PU)

RPU_100K

Vin=OVDD

—

μA

Pull-down resistor (100 k

Ω PD)

RPD_100K

Vin=OVDD

—

μA

Pull-down resistor (100 k

Ω PD)

RPD_100K

Vin=0V

—

μA

Keeper Circuit Resistance

Rkeep

—

105

165

Input current (no pull-up/down)

Iin

VI = 0,VI = OVDD

-2.9

2.9

μA

Input Mode Selection: SW_PAD_CTL_GRP_DDR_TYPE_RGMII = 10 (1.8V Mode)

SW_PAD_CTL_GRP_DDR_TYPE_RGMII = 11 (2.5V Mode).

2 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6

V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must

be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

3 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.

4 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled

(register IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC[HYS]= 0).

Table 23. LPDDR2 I/O DC Electrical Parameters1

Parameters

Symbol

Test Conditions

Min

Max

Unit

High-level output voltage

Voh

Ioh = -0.1 mA

0.9

× OVDD

—

Low-level output voltage

Vol

Iol = 0.1 mA

—

0.1

× OVDD

Input reference voltage

Vref

—

0.49

× OVDD

0.51

× OVDD

DC input High Voltage

Vih(dc)

—

Vref+0.13V

OVDD

DC input Low Voltage

Vil(dc)

—

OVSS

Vref-0.13V

Differential Input Logic High

Vih(diff)

—

0.26

See Note 2

—

Differential Input Logic Low

Vil(diff)

—

See Note 2

-0.26

—

Input current (no pull-up/down)

Iin

Vin = 0 or OVDD

-2.5

2.5

μA

Table 22. RGMII I/O 2.5V I/O DC Electrical Parameters1 (continued)

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