IMX7ULPCECB2 datasheet(29/122 Pages) NXP

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4.1.1 Internal memory—real-time domain

The real-time domain contains 256 kB of SRAM organized in sub-blocks of 32 kB

each. Each sub-block can be power-gated under software control to optimize power

consumption.

4.1.2 QuadSPI flash

The Quad Serial Peripheral Interface (QSPI) module provides an interface to various

types of serial flash memory. It allows one serial flash connection and supports 1-bit,

4-bit and 8-bit SPI bus width.

4.2 Peripherals—real-time domain

4.2.1 Analog—real-time domain

The i.MX 7ULP Real-Time Domain implements the following analog peripherals:

• 12-bit Analog to Digital Converter

• 12-bit Digital to Analog Converter

• Comparators

See i.MX 7ULP modules list for more details.

4.2.2 Connectivity and communications—real-time domain

The i.MX 7ULP Real-Time Domain implements the following connectivity and

communications peripherals:

• Low Power Universal Asynchronous Receiver/Transmitter (LPUART)

• Low Power Inter-Integrated Circuit (LPI2C)

• Low Power Serial Peripheral Interface (LPSPI)

• Rapid General-Purpose Input and Output with 2 Ports (RGPIO2P)

• Flexible Input/Output (FlexIO)

See the i.MX 7ULP modules list for more details.

5 System control modules

System control modules

i.MX 7ULP Applications Processor—Consumer, Rev. 0, 09/2020

NXP Semiconductors

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