ADUC7121BBCZ datasheet(21/102 Pages) AD

21 / 102 page

Data Sheet

ADuC7120/ADuC7121

Rev. D | Page 21 of 102

Pin No.

Mnemonic

Type1

Description

P0.2/SPICLK/ADCBUSY/PLAO[13]

I/O

General-Purpose Input and Output Port 0.2 (P0.2).

SPI Clock (SPICLK).

Status of the ADC (ADCBUSY).

Programmable Logic Array for Output Element 13 (PLAO[13]).

P3.0/PLAO[0]

I/O

General-Purpose Input and Output Port 3.0 (P3.0).

Programmable Logic Array for Output Element 0 (PLAO[0]).

PVDD_IDAC3

2.0 V Power for the IDAC3.

PVDD_IDAC4

2.0 V Power for IDAC4.

AVDD

Analog Supply (3.3 V).

CDAMP_IDAC2

Damping Capacitor Pin for IDAC2.

P2.7/PLAI[0]

I/O

General-Purpose Input and Output Port 2.7 (P2.7).

Programmable Logic Array for Input Element 0 (PLAI[0]).

C10

P1.2/TDI/PLAO[15]

General-Purpose Input and Output Port 1.2 (P1.2).

JTAG Test Port Input, Test Data In (TDI). The TDI function of Pin C10 is for debug and

download access.

Programmable Logic Array for Output Element 15 (PLAO[15]).

C11

P3.1/PLAO[1]

I/O

General-Purpose Input and Output Port 3.1 (P3.1).

Programmable Logic Array for Output Element 1 (PLAO[1]).

C12

RST

Reset Input (Active Low).

P3.2/IRQ4/PWM3/PLAO[2]

I/O

General-Purpose Input and Output Port 3.2 (P3.2).

External Interrupt Request 4, Active High (IRQ4).

Pulse-Width Modulator 3 Output (PWM3).

Programmable Logic Array for Output Element 2 (PLAO[2]).

P1.1/SOUT/SDA1/PLAI[6]

I/O

General-Purpose Input and Output Port 1.1 (P1.1).

Serial Output, Transmit Data, UART (SOUT).

I2C Interface Serial Data for I2C1 (SDA1).

Programmable Logic Array for Input Element 6 (PLAI[6]).

P0.3/MISO/PLAO[12]/SYNC

I/O

General-Purpose Input and Output Port 0.3 (P0.3).

SPI Master In Slave Out (MISO).

Programmable Logic Array for Output Element 12 (PLAO[12]).

Synchronous Reset (SYNC). Input to reset synchronously the PWM counters using an

external source.

D10

P1.3/TDO/PLAO[14]

General-Purpose Input and Output Port 1.3 (P1.3).

JTAG Test Port Output, Test Data Out (TDO). The TDO function of Pin D10 is for debug

and download access.

Programmable Logic Array for Output Element 14 (PLAO[14]).

D11

P0.0/SCL0/PLAI[5]

I/O

General-Purpose Input and Output Port 0.0 (P0.0).

I2C Interface Serial Clock for I2C0 (SCL0).

Programmable Logic Array for Input Element 5 (PLAI[5]).

D12

P3.6/PLAO[10]

I/O

General-Purpose Input and Output Port 3.6 (P3.6).

Programmable Logic Array for Output Element 10 (PLAO[10]).

P3.3/IRQ5/PWM4/PLAO[3]

I/O

General-Purpose Input and Output Port 3.3 (P3.3).

External Interrupt Request 5, Active High (IRQ5).

Pulse-Width Modulator 4 Output (PWM4).

Programmable Logic Array for Output Element 3 (PLAO[3]).

P3.4/PLAO[8]

I/O

General-Purpose Input and Output Port 3.4 (P3.4).

Programmable Logic Array for Output Element 8 (PLAO[8]).

P0.4/MOSI/PLAI[11]/TRIP

I/O

General-Purpose Input and Output Port 0.4 (P0.4).

SPI Master Out Slave In (MOSI).

Programmable Logic Array for Input Element 11 (PLAI[11]).

PWM Trip Interrupt (TRIP). The TRIP function of Pin E3 is the input that allows the PWM

trip interrupt to be triggered.

E10

TMS

JTAG Test Port Input, Test Mode Select. Debug and download access.

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