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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.3

03-Feb-2021

CFR0011-120-00

66 of 94

9.9

GPIO

All digital pads can be used as GPIO, and each GPIO port is mixed with a multi-functional interface.

The GPIO features of DA16200 are listed below:

■ Input or output lines in a programmable direction

■ Word and half word read/write access

■ Address-masked byte writes to facilitate quick bit set and clear operations

■ Address-based byte reads to facilitate quick bit test operations

■ Maskable interrupt generation based on input value change

■ Possible to be output signal of PWM[3:0], external interrupt, QSPI_CSB[3:1], RF_SW[1:0], and

UART_TXDOE[2:0] on the GPIO pins:

□ It provides special functions for GPIO pin use. PWM [3:0], external interrupt, QSPI_CSB [3:1],

RF_SW [1:0], and UART_TXDOE [2:0] signals can be output by selecting unused pins

among the GPIO pins. It is possible to select the function to be output from the GPIO register

setting and select the remaining GPIO pin without using it to output the specific function to

the desired GPIO pins

9.9.1

Antenna Switching Diversity

DA16200 provides the antenna switching diversity function for performance improvement in a multi-

path environment. A PHY block measures the RSSI of each antenna and selects the antenna with

the largest RSSI. The selected antenna is also used for transmission. To use this function, an

external switching element is required, and switching control is done through the GPIO. Two GPIOs

can be used for switching control, and for this purpose any unused pins among the GPIO pins can be

selected. The control signal can be changed by register setting to suit the external switching device.

RF Switch

DA16200

GPIO

ANT

Antenna1

Antenna2

Figure 45: Antenna Switching Internal Block Diagram

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