MDS 556-04 C

2

Revision 030905

ICS556-04

Pin Assignment

Pin Descriptions

External Components

A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01

µF

should be connected between VDD on pin 1 and GND on pin 4, as close to the device as possible. A 33

Ω series

terminating resistor may be used on each clock output if the trace is longer than 1 inch.

To achieve the low output skew that the ICS556-04 is capable of, careful attention must be paid to board layout.

Essentially, all four outputs must have identical terminations, identical loads, and identical trace geometries. If not,

the output skew will be degraded. For example, using a 30

Ω series termination on one output (with 33Ω on the

others) will cause at least 15 ps of skew.

Crystal Information

The crystal used should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors

should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these

capacitors is given by the following equation:

Crystal caps (pF) = (CL - 6) x 2

In the equation, CL is the crystal load capacitance. So, for a crystal with a 16 pF load capacitance, two 20 pF [(16-6)

x 2] capacitors should be used.

1

2

3

X 1 /ICL K

4

VDD

GND

Q4

Q3

8

7

6

5

X2

8- pi n ( 150 mi l ) S OI C

Q1

Q2

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

VDD

Power

Connect to +2.5 V, +3.3 V or +5.0 V.

2

X1/ICLK

Input

Crystal or clock input (5 V tolerant input). Connect to 5 to 27 MHz input.

3

X2

Input

Connect to a fundamental mode crystal. Leave open for clock input.

4

GND

Power

Connect to ground.

5

Q1

Output

Clock Output 1.

6

Q2

Output

Clock Output 2.

7

Q3

Output

Clock Output 3.

8

Q4

Output

Clock Output 3.