ICS525-01RT datasheet(7/9 Pages) ICST

7 / 9 page

User Configurable Clock

MDS 525-01/02/11/12 Q

Revision 101105

Integrated Circuit Systems, Inc.

● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

ICS525-01/02/11/12

AC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V

Short Circuit Current

CLK and REF outputs

±55

Input Capacitance

CIN

V, R, S pins and pin 19

On-chip Pull-up Resistor

RPU

V, R, S pins and pin 19

270

Ω

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

FIN

Crystal input

MHz

Clock input

MHz

Output Clock Rise Time

0.8 to 2.0 V

Output Clock Fall Time

2.0 to 0.8 V

Output Clock Duty Cycle, OD =

2, 4, 6, 8, or 10

At VDD/2

49 to

Output Clock Duty Cycle, OD =

3, 5, 7, or 9

At VDD/2

Output Clock Duty Cycle, OD =

1 (-02 and -12 only)

At VDD/2

Power-down Time, PD low to

clocks stopped

Power-up Time, PD high to

clocks stable

Absolute Clock Period Jitter,

ICS525-01, Note 2

tja

Deviation from mean

±140

One Sigma Clock Period Jitter,

ICS525-01, Note 2

tjs

One Sigma

Absolute Clock Period Jitter,

ICS525-02, Note 2

tja

Deviation from mean

±85

One Sigma Clock Period Jitter,

ICS525-02, Note 2

tjs

One Sigma

Absolute Clock Period Jitter,

ICS525-11, Note 2

tja

Deviation from mean

±160

One Sigma Clock Period Jitter,

ICS525-11, Note 2

tjs

One Sigma

Absolute Clock Period Jitter,

ICS525-12, Note 2

tja

Deviation from mean

±160

One Sigma Clock Period Jitter,

ICS525-12, Note 2

tjs

One Sigma

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

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