Quad PLL Field Programmable VersaClock Synthesizer

MDS 348-22 A

2

Revision 120704

Integrated Circuit Systems, Inc.

ICS348-22

PRELIMINARY INFORMATION

Pin Assignment

Output Configuration Table

16

1

15

2

14

X1

X2

3

13

S0

4

12

S1

VDD

5

11

CLK9

6

PDTS

7

VDD

8

GND

S2

VDD

GND

CLK1

CLK5

CLK2

CLK6

9

10

CLK3

CLK7

CLK4

CLK8

20

19

18

17

20-pin (150 mil) SSOP (QSOP)

S2 S1 S0

Outputs

0

0

0 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz

0

0

1 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz

0

1

0 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz

0

1

1 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz

1

0

0 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz

1

0

1 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz

1

1

0 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz

1

1

1 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=OFF, CLK8=189 MHz, CLK9=127 MHz