ICS421-05 datasheet(2/5 Pages) ICST

2 / 5 page

DIGITAL VIDEO CAMERA CLOCK

MDS 421-05 B

Revision 072304

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ●

www.icst.com

ICS421-05

Pin Assignment

OE_USB Operation Table

Pin Descriptions

External Components

Series Termination Resistor

Clock output traces over one inch should use series

termination. To series terminate a 50

Ω trace (a

commonly used trace impedance), place a 33

Ω resistor

in series with the clock line, as close to the clock output

pin as possible. The nominal impedance of the clock

output is 20

Ω.

Decoupling Capacitor

As with any high-performance mixed-signal IC, the

ICS421-05 must be isolated from system power supply

noise to perform optimally.

A decoupling capacitor of 0.01µF must be connected

between VDD and the PCB ground plane.

PCB Layout Recommendations

For optimum device performance and lowest output

phase noise, the following guidelines should be

observed.

1) The 0.01µF decoupling capacitor should be mounted

on the component side of the board as close to the

VDD pin as possible. No vias should be used between

decoupling capacitor and VDD pin. The PCB trace to

VDD pin should be kept as short as possible, as should

the PCB trace to the ground via. Distance of the ferrite

bead and bulk decoupling from the device is less

critical.

2) To minimize EMI, the 33

Ω series termination resistor

(if needed) should be placed close to the clock output.

3) An optimum layout is one with all components on the

same side of the board, minimizing vias through other

signal layers (the ferrite bead and bulk decoupling

capacitor can be mounted on the back). Other signal

traces should be routed away from the ICS421-05. This

includes signal traces just underneath the device, or on

layers adjacent to the ground plane layer used by the

device.

CLKIN

VDD

GND

12M

24.576M

VDD

72M

OE_USB

8 pin (173 mil) TSSOP

OE_USB

Function

Output tri-state

Output running

Number

Name

Type

Pin Description

CLKIN

Input

27 MHz single ended clock input.

VDD

Power

Connect to voltage supply.

GND

Power

Connect to ground.

24.576M

Output

24.576 MHz clock output.

72M

Output

72 MHz clock output for CCD.

VDD

Power

Connect to voltage supply.

12M

Output

12 MHz clock output for USB.

OE_USB

Input

Output enable for 12M clock for USB. See table for functionality,

internal pull-down.

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