Quad PLL Field Programmable VersaClock Synthesizer

MDS 348-22 A

3

Revision 120704

Integrated Circuit Systems, Inc.

ICS348-22

PRELIMINARY INFORMATION

Pin Descriptions

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

X1

XI

Crystal Input. Connect this pin to a 25 MHz crystal.

2

S0

Input

Select pin 0. Internal pull-up resistor.

3

S1

Input

Select pin 1. Internal pull-up resistor.

4

CLK9

Output

127 MHz output clock. Weak internal pull-down when tri-state.

5VDD

Power

Connect to +3.3 V.

6

GND

Power

Connect to ground.

7

CLK1

Output

127 MHz output clock. Weak internal pull-down when tri-state.

8

CLK2

Output

127 MHz output clock. Weak internal pull-down when tri-state.

9

CLK3

Output

127 MHz output clock. Weak internal pull-down when tri-state.

10

CLK4

Output

127 MHz output clock. Weak internal pull-down when tri-state.

11

CLK8

Output

189 MHz output clock. Weak internal pull-down when tri-state.

12

CLK7

Output

187 MHz output clock. Weak internal pull-down when tri-state.

13

CLK6

Output

187 MHz output clock. Weak internal pull-down when tri-state.

14

CLK5

Output

127 MHz output clock. Weak internal pull-down when tri-state.

15

GND

Power

Connect to ground.

16

VDD

Power

Connect to +3.3 V.

17

S2

Input

Select pin 2. Internal pull-up resistor.

18

PDTS

Input

Power down tri-state. Powers down entire chip and tri-states clock outputs

when low. Internal pull-up resistor.

19

VDD

Power

Connect to +3.3 V.

20

X2

XO

Crystal Output. Connect this pin to a fundamental crystal. Float for clock input.