STCC02-E datasheet(3/13 Pages) STMICROELECTRONICS

3 / 13 page

STCC02-ED5

3/13

Its output voltage accuracy, that contributes to the ADC accuracy of the MCU, is better than ± 10 % in the

whole operating range of the temperature TAMB, the load current IDD and the input voltage VIN. The

STCC02 input voltage range from 7 to 27 V; and its DC output current is less than 20 mA to keep the inter-

nal dissipation compatible with thermal package capability.

The regulator includes also an over current limiter to prevent high current conditions during the power up

inrush or the output short circuit. This limiter is made of a serial shunt resistance as current sensor and a

circuit that regulates the input over current.

■ The reset circuit

This circuit ensures a Low Voltage Detection (LVD) of the output voltage of the regulator. Most micro-

controllers have an active RESET pin in the low state: so, the /RST pin will be active at low state.

The reset circuit senses the regulator voltage VDD. Its comparator with hysteresis achieves this task.

The /RST pin is high when VDD is higher than the high threshold VH = 4.25 V; and is low when the VDD

decreases below the low threshold VL = 3.75 V.

The comparator output changes are filtered for a high immunity. When the reset is disabling (VDD > VH),

the /RST signal rises after the delay time TUP. This delay is set by an external capacitor CUP connected

to the DLC pin: TUP = 6 ms for CUP = 47 nF.

When the reset is enabling (VDD < VL), the /RST signal is falling after a delay time TDW that is internally

set at 40

µs when CUP = 47 nF.

■ The Zero Voltage Synchronization ZVS Circuit

DLC

If C

= 47 nF, T

= 6 ms

External

Capacitor

CUP

/RST

PROGRAMMABLE

DELAY

NOISE FILTER

VDD

V = 4.25 V

500

Ω

V = 3.75 V

DW ~ 40 µs

circuit output

internal latch output

UP = 6 ms

UP = 47 nF

RST\

DW ~ 40 µs

circuit output

internal latch output

UP = 6 ms

UP = 47 nF

RST\

VCC

VDD

ZVS

VZVS

VTF

COM

100 k

Ω

500

Ω

25 k

Ω

SYN

20 µs Filter

RZV

LINE

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