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LTC1411

1411f

Single Supply

14-Bit 2.5Msps ADC

The LTC

verter in a 36-pin SSOP package, which typically dissi-

pates only 195mW from a single 5V supply. This device

comes complete with a high bandwidth sample-and-

hold, a precision reference, programmable input ranges

and an internally trimmed clock. The ADC can be powered

down with either the Nap or Sleep mode for low power

applications.

The LTC1411 converts either differential or single-ended

inputs and presents data in 2’s complement format.

Maximum DC specs include

±2LSB INL and 14-bit no

missing code over temperature. Outstanding dynamic

performance includes 80dB S/(N + D) and 90dB THD at

100kHz input frequency.

The LTC1411 has four programmable input ranges se-

lected by two digital input pins, PGA0 and PGA1. This

provides input spans of

±1.8V,±1.27V,±0.9Vand±0.64V.

An out-of-the-range signal together with the D13 (MSB)

will indicate whether a signal is over or under the ADC’s

input range. A simple conversion start input and a data

ready signal ease connections to FIFOs, DSPs and micro-

processors.

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Sample Rate: 2.5Msps

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Single 5V Operation

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No Pipeline Delay

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Programmable Input Ranges

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Low Power Dissipation: 195mW (Typ)

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True Differential Inputs Reject Common Mode Noise

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Out-of-Range Indicator

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Internal or External Reference

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Sleep (1

µA) and Nap (2mA) Shutdown Modes

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36-Pin SSOP Package

, LTC and LT are registered trademarks of Linear Technology Corporation.

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Telecommunications

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High Speed Data Acquisition

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Digital Signal Processing

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Multiplexed Data Acquisition Systems

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Spectrum Analysis

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Imaging Systems

OTR

D13

OGND

DVP

CONTROL LOGIC

2.5V

BANDGAP

REFERENCE

INTERNAL

CLOCK

14-BIT

ADC

OUTPUT

DRIVERS

REFOUT

14

+

–

PGA0

PGA1

CONVST

DGND

1411 BD

+

–

NAP

SLP

•

•

•

AVM

7, 8, 9

3

REFIN

2k

5k

5k

2

1

32

33

34

35

36

11

AGND

31

26

BUSY

27

D0

25

12

28

29

30

4

REFCOM1

5

REFCOM2

6

X1.62/

X1.15

AVP

10

FEATURES

DESCRIPTIO

APPLICATIO S

BLOCK DIAGRA

INPUT FREQUENCY (kHz)

10

38

50

62

100

1000

10000

1411 TA02

26

14

86

74

32

44

56

20

80

68

10

14

12

13

11

S/(N + D) and Effective Bits

vs Input Frequency