AT45DB081E datasheet(21/79 Pages) DIALOG

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AT45DB081E

DS-AT45DB081E–028K–03-2021

The device also incorporates an intelligent algorithm that can detect when a byte location fails to erase properly. If

an erase error arises, it is indicated by the EPE bit in the Status Register.

Table 7-2.

Sector Erase Addressing

7.10 Chip Erase

The Chip Erase command allows the entire main memory array to be erased can be erased at one time.

To execute the Chip Erase command, a four-byte command sequence of C7h, 94h, 80h, and 9Ah must be clocked

into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the

device, and any data clocked in after the opcode is ignored. After the last bit of the opcode sequence has been

clocked in, the CS pin must be deasserted to start the erase process. The erase operation is internally self-timed

and takes a time of tCE. During this time, the RDY/BUSY bit in the Status Register indicates that the device is busy.

The Chip Erase command does not affect sectors that are protected or locked down; the contents of those sectors

remain unchanged. Only those sectors that are not protected or locked down are erased.

The WP pin can be asserted while the device is erasing, but protection is not activated until the internal erase cycle

completes.

The device also incorporates an intelligent algorithm that can detect when a byte location fails to erase properly. If

an erase error arises, it is indicated by the EPE bit in the Status Register.

Table 7-3.

Chip Erase Command

Figure 7-1. Chip Erase

PA11/

A19

PA10/

A18

PA9/

A17

PA8/

A16

PA7/

A15

PA6/

A14

PA5/

A13

PA4/

A12

PA3/

A11

PA2/

A10

PA1/

PA0/

Sector

•

Command

Byte 1

Byte 2

Byte 3

Byte 4

Chip Erase

C7h

94h

80h

9Ah

C7h

94h

80h

9Ah

Each transition represents eight bits

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