AT25XE321D datasheet(48/124 Pages) DIALOG

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Datasheet

2021-Aug-2

DS-AT25XE321D-160

Revision J

AT25XE321D

Datasheet

32-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory

with Multi-I/O Support

5.7 STATUS REGISTER 5

The following table shows the bit assignments for Status register 5.

Table 18: Status Register 5 Format

Bit #

Acronym

Name

Type

Default

Description

SRLOCK

Status Register

Lock

Hardware sets this bit when the user executes the Status

two verification bytes, 4Dh and 67h. Once this action oc-

curs, the Status registers can be permanently locked.

6:4

DC[2:0]

Dummy Clocks

R/W

000

This field indicates the number of dummy clocks to be in-

serted between the address and data transactions for the

EBh and E7h commands. Note that the dummy clocks in-

clude the 2 clocks required to clock in the M[7:0] bits.

000: 2 clocks

001: 4 clocks

010: 6 clocks

011: 8 clocks

100: 10 clocks.

101 - 111: Reserved

Erase Suspend

This bit is set by hardware whenever an erase operation is

suspended.

Program Suspend

This bit is set by hardware whenever a program operation

is suspended.

TERE

Terminate Enable

R/W

The TERE bit enables or disables the Terminate command.

Its encoding is:

0: Terminate command is disabled

1: Terminate command is enabled

When the TERE bit is cleared (the default state after power-

up), the Terminate command is disabled and any attempts

to reset the device using the Terminate command are ig-

nored. When the TERE bit is set, the Terminate command

is enabled.

The TERE bit retains its state as long as power is applied

to the device. Once set, the TERE bit remains in that state

until it is modified using the Write Status Register Byte 5

command or until the device has been power cycled.

DWA

Doubleword

Aligned

R/W

Setting the DWA bit indicates that the devices adheres to

double-word aligned addressing. This bit is only used when

the EBh (XiP DWA Read) command is executed and is

encoded as follows:

0: Double-word addressing is disabled

1: Double-word addressing is enabled

When this bit is set, the lower 2 bits of address are ignored

and assumed to be 00.

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