AT25SL641-DWF datasheet(21/76 Pages) DIALOG

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AT25SL641

DS-25SL641–113F–12/2018

edge of SCK with most significant bit (MSB) first as shown in (Figure 7-4 and Figure 7-5). The Status Register can be read

continuously. The instruction is completed by driving CS high.

Figure 7-4.

Read Status Register Instruction (SPI Mode)

Figure 7-5.

Read Status Register Instruction (QPI Mode)

7.6

Write Status Register (01h)

The Write Status Register instruction is u s e d to write the non-volatile Status Register-1 bit (SRP0) and Status

Status Register instruction.

A Write Enable instruction must previously have been issued prior to setting Write Status Register Instruction (Status

instruction code, and then writing the status register data byte as illustrated in Figure 7-6 and Figure 7-7.

The CS pin must be driven high after either the eighth or sixteenth bit of data is clocked in. If this is not done, the Write

Status Register instruction will not be executed. If CS is driven high after the eighth clock, the CMP, QE, and SRP1 bits

are cleared to 0. After CS is driven high, the self-timed Write Status Register cycle commences for a time duration of t

(See AC Characteristics).

While the Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to

check the status of the BUSY bit. The BUSY bit is d r i v e n h i g h during the Write Status Register cycle and

d r i v e n l o w when the cycle has finished and is ready to accept other instructions. When the BUSY bit is asserted,

the Write Enable Latch (WEL) bit in Status Register is cleared to 0.

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