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AT25SL321

DS-25SL321–112H–2020-10

8.6

Write Status Register (01h)

The Write Status Register instruction is to write the non-volatile Status Register-1 bit (SRP0) and Status

Write Status Register instruction.

A Write Enable (06h) instruction must have been previously issued prior to setting Write Status Register

Instruction (Status Register bit WEL = 1). Once the write is enabled, the instruction is entered by driving CS low,

sending the instruction code, and then writing the status register data byte as illustrated in Figure 8-6 and Figure 8-

The CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done the

Write Status Register instruction can not be executed. If CS is driven high after the eighth clock, hardware clears

the CMP, QE and SRP1 bits to 0. After CS is driven high, the self- timed Write Status Register cycle commences

for a time duration of tw (See AC Characteristics).

While the Write Status Register cycle is in progress, the Read Status Register instruction can still be accessed to

check the status of the BUSY bit. The BUSY bit is set during the Write Status Register cycle and cleared

when the cycle is finished to indicate the device is ready to accept other instructions. When the BUSY bit is

asserted, the Write Enable Latch (WEL) bit in Status Register is cleared to 0.

Figure 8-6. Write Status Register Instruction (SPI Mode)

Figure 8-7. Write Status Register Instruction (QPI Mode

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