AT25SF321B datasheet(28/61 Pages) DIALOG

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AT25SF321B

DS-AT25SF321B–179E–06-2020

Protection Commands and Features

9.1

Write Enable (06h)

The Write Enable command sets the Write Enable Latch (WEL) bit in the Status Register to a logical “1” state. The

WEL bit must be set before a Byte/Page Program, Erase, Program Security Register Pages, Erase Security

a two step process, thus reducing the chances of a command being accidentally or erroneously executed. If the

WEL bit in the Status Register is not set prior to the issuance of one of these commands, the command is not

executed.

To issue the Write Enable command, the CS pin must first be asserted, and the opcode of 06h must be clocked

into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode is

ignored. When the CS pin is deasserted, the WEL bit in the Status Register is set to a logical “1”. The complete

opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an

byte boundary (multiples of eight bits); otherwise, the device aborts the operation, and the WEL bit state does not

change.

Figure 9-1. Write Enable Timing

9.2

Write Disable (04h)

The Write Disable command resets the Write Enable Latch (WEL) bit in the Status Register to the logical “0” state.

With the WEL bit reset, all Byte/Page Program, Erase, Program Security Register Page, and Write Status Register

commands are not executed. Other conditions can also cause the WEL bit to be reset; for more details, see the

WEL bit section of the Status Register description (Section 9.1).

To issue this command, the CS pin must be asserted first, and the opcode of 04h must be clocked into the device.

No address bytes need to be clocked into the device, and any data clocked in after the opcode is ignored. When

the CS pin is deasserted, the WEL bit in the Status Register is reset to a logical “0”. The complete opcode must be

clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an byte boundary

(multiples of eight bits); otherwise, the device aborts the operation, and the WEL bit state does not change.

Figure 9-2. Write Disable Timing

SCK

MSB

00000110

OPCODE

HIGH-IMPEDANCE

SCK

MSB

00000100

OPCODE

HIGH-IMPEDANCE

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