PLL520-40

CMOS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1

FEATURES

• 65MHz to 130MHz Fundamental Mode Crystal.

• Output range: 65MHz – 130MHz (no PLL).

• Low Injection Power for crystal 50uW.

• CMOS outputs (High Drive (30mA) or Standard

Drive (10mA) output).

• Integrated variable capacitors.

• Supports 2.5V or 3.3V-Power Supply.

• Available in die form.

• Thickness 10 mil.

DESCRIPTION

The PLL520-40 is a VCXO IC specifically designed

to pull frequency fundamental crystals from 65MHz

to 130MHz, with CMOS outputs. Its design was

optimized to tolerate higher limits of interelectrode

capacitance and bonding capacitance to improve

yield. It achieves very low current into the crystal

resulting in better overall stability. Its internal

varicaps allow an on chip frequency pulling,

controlled by the VCON input.

BLOCK DIAGRAM

DIE CONFIGURATION

DIE SPECIFICATIONS

Name

Value

Size

62 x 65 mil

Reverse side

GND

Pad dimensions

80 micron x 80 micron

Thickness

10 mil

DRIVE_SEL AND OE_CTRL TABLE

DRIVE_SEL

(Pad #19)

Output Drive

0

High Drive CMOS

1

Standard CMOS (default)

OE_CTRL

(Pad #30)

State

0

Tri-state

1

Output enabled (default)

18

19

20

21

23

25

7

13

10

26

29

31

Y

X

(0,0)

(1550,1475)

65 mil

24

22

17

16

15

14

12

11

9

8

6

1

2

3

45

27

28

30

N/C

CMOS

N/C

VDDBUF

VDDBUF

N/C

N/C

CMOS

GNDBUF

XIN

XOUT

VCON

OE

CTRL^

N/C

N/C

Die ID:

A1313-13C

C502A

Note: ^ denotes internal pull up

XIN

XOUT

OE

Q

PLL520-40

Amplifier

w/

integrated

varicaps