AT25QF641-DWF datasheet(21/74 Pages) DIALOG

tên linh kiện	AT25QF641-DWF

Giải thích chi tiết về linh kiện	64-Mbit, 2.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

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AT25QF641

DS-25QF641–127E–3/2018

Figure 7-8.

Write Status Register-2 Instruction (SPI Mode)

Figure 7-9.

Write Status Register-2 Instruction (QPI Mode)

7.8

Read Data (03h)

The Read Data instruction is to read data out from the device. The instruction is initiated by driving the CS pin low and then

sending the instruction code “03h” with following a 24-bit address (A23- A0) into the SI pin. After the address is received, the

data byte of the addressed memory location will be shifted out on the SO pin at the falling edge of SCK with most significant bit

(MSB) first. The address is automatically incremented to the next higher address after byte of data is shifted out allowing for a

continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock

continues. The instruction is completed by driving CS high. The Read Data instruction sequence is shown in Figure 7-10. If a

Read Data instruction is issued while an Erase, Program or Write Status Register cycle is in process (BUSY = 1) the instruction

is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D.C to a

maximum of

R (see Section , ).

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