Preliminary

PLL103-06

DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 12/20/00 Page 2

PIN DESCRIPTIONS

Name

Number

Type

Description

FBOUT

1

O

Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V.

BUF_IN

10

I

Reference input from chipset. 3.3V input for STANDARD SDRAM mode;

2.5V input for DDR-ONLY mode.

PD

2

I

Power Down Control input. When low, it will tri-state all outputs.

SEL_DDR

28

I

Input configure for DDR-ONLY mode or STANDARD SDR mode.

1 = DDR-ONLY mode (when VDD3.3_2.5 select 2.5V);

0 = SDR mode (when VDD3.3_2.5 select 3.3V).

In DDR-ONLY mode, all outputs will be configured as DDR outputs.

In STANDARD SDR mode, all outputs will be configured as SDRAM

outputs.

DDR[0:5]T_SDRAM

[0,2,4,6,8,10]

3,7,12,19,

23,27

O

When SEL_DDR=1, these outputs provide DDR mode outputs; when

SEL_DDR=0, these outputs provide standard SDRAM mode outputs.

Voltage swing depends on VDD3.3_2.5.

DDR[0:5]C_SDRAM

[1,3,5,7,9,11]

4,8,13,18,

22,26

O

When SEL_DDR=1, these outputs provide complementary copies of

BUF_IN; when SEL_DDR=0, these outputs provide standard SDRAM

mode outputs. Voltage swing depends on VDD3.3_2.5.

VDD3.3_2.5

5,9,14,21,25

P

When VDD=2.5V, SEL_DDR=1. DDR-ONLY mode is selected; when

VDD=3.3V, SEL_DDR=0. STANDARD SDRAM mode is selected.

GND

6,11,17,

20,24

P

Ground.