CY25245
Document #: 38-07124 Rev. *B
Page 3 of 11
Overview
The CY25245 product is one of a series of devices in the
Cypress PREMIS family. The PREMIS family incorporates the
latest advances in PLL spread spectrum frequency synthe-
sizer techniques. By frequency modulating the output with
a low-frequency carrier, peak EMI is greatly reduced. Use of
this technology allows systems to pass increasingly difficult
EMI testing without resorting to costly shielding or redesign.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The
Simplified Block Diagram shows a simple implementation.
Functional Description
The CY25245 uses a phase-locked loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
times the reference frequency.[3] The unique feature of the
Spread Spectrum Frequency Timing Generator is that a
modulating waveform is superimposed at the input to the VCO.
This causes the VCO output to be slowly swept across a
predetermined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum
process has little impact on system performance.
Frequency Selection With SSFTG
In spread spectrum frequency timing generation, EMI
reduction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Using frequency select bits (FS2:1 pins), the frequency range
can be set (see Table 2). Spreading percentage is set with pins
MW0:2 as shown in Table 2.
A larger spreading percentage improves EMI reduction.
However, large spread percentages may either exceed
system maximum frequency ratings or lower the average
frequency to a point where performance is affected. For these
reasons, spreading percentage options are provided.
Note:
3. For the CY25245, the output frequency is nominally equal to the input frequency.
Table 2. Modulation Width Selection Table
EMI Reduction
Modulation Setting
Bandwith Limit Frequencies as a % Value of Fout
MW0 = 0
MW0 = 1
MW2
MW1
Low
High
Low
High
Minimum EMI Control
0
0
98.75%
100%
99.375%
100.625%
Suggested Setting
0
1
97.5%
100%
98.75%
101.25%
Alternate Setting
1
0
95.0%
100%
97.5%
102.5%
Maximum EMI reduction
1
1
90.0%
100%
95%
105%
Freq.
Phase
Modulating
VCO
Post
CLKOUT
Detector
Charge
Pump
Waveform
Dividers
Divider
Feedback
Divider
PLL
GND
VDD
Σ
Q
P
Clock Input
Reference Input
(EMI suppressed)
Figure 1. Functional Block Diagram
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