FXLS8967AF datasheet(14/98 Pages) NXP

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NXP Semiconductors

FXLS8967AF

3-Axis Low-g Accelerometer

aaa-040836

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

SDA

SCL

9th clock

1st clock cycle

9th clock

1 / fSCL

tLOW

tSET

tSU:DAT

tSU:STA

tHD:STA

tSU:STO

tVD:ACK

tBUF

tSP

tHIGH

tVD:DAT

tHD:DAT

continued

Figure 4. I2C secondary timing diagram for Standard-mode, Fast-mode and Fast-mode Plus

12.1.1 General I2C operation

There are two signals associated with the I2C-bus: the Serial Clock Line (SCL) and the

Serial Data line (SDA). SDA is a bidirectional signal used for sending and receiving the

data to/from the interface. External pull-up resistors connected to VDD are required for

SDA and SCL. When the I2C-bus is free, SCL and SDA are high.

The maximum practical operating frequency for I2C in a given system implementation

depends on several factors including the pull-up resistor and voltage values and total bus

capacitance (PCB trace + parasitic device capacitances).

The primary starts a transaction on the bus through a start condition (ST) signal, which

is defined as a HIGH-to-LOW transition on SDA line while the SCL line is held HIGH.

After the primary transmits the ST signal, the bus is considered busy. The next byte of

data transmitted contains the secondary address in the first seven bits, and the eighth bit,

the read/write bit, indicates whether the primary is receiving data from the secondary or

transmitting data to the secondary. When an address is sent, each device in the system

compares the first seven bits after the ST condition with its own address. If they match,

the device considers itself addressed by the primary. The ninth clock pulse, following the

secondary address byte (and each subsequent byte) is the acknowledge (ACK). The

transmitter must release the SDA line during the ACK period. The receiver must then pull

the data line low so that it remains stable low during the high period of the acknowledge

clock period.

The number of bytes per transfer is unlimited. If a receiver cannot receive another

complete byte of data until it has performed some other function, it can hold the SCL

line low to force the transmitter into a wait state. Data transfer only continues when the

receiver is ready for another byte and releases the clock line. This delay action is called

clock stretching. Not all primary devices support clock stretching. This device implements

clock stretching—the SCL line may be stretched (pulled low) for up to 1 µs when needed

FXLS8967AF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 27 April 2021

14 / 98

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