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FXLS90130 bảng dữ liệu(PDF) 49 Page - NXP Semiconductors

tên linh kiện FXLS90130
Giải thích chi tiết về linh kiện  Single channel inertial sensor
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FXLS90130 bảng dữ liệu(HTML) 49 Page - NXP Semiconductors

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NXP Semiconductors
FXLS9xxx0
Single channel inertial sensor
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$05
COMMREV
0
0
0
0
COMMREV[3:0]
Reset Value for DSI3
0
0
0
0
0
0
0
1
Reset Value for PSI5
0
0
0
0
0
1
1
0
Reset Value for SPI
0
0
0
0
0
0
0
0
Reset Value for I2C
0
0
0
0
0
1
0
1
Table 69. Communication protocol revision register (COMMREV)
Note: The response to a register write of the COMMREV register is a valid response
with the register contents equal to 0x00.
11.2.4 Margin read status register (MREAD_STAT)
The Margin Read Status register is a read-only register which contains the status for the
user enabled OTP margin read test.
This register is readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming
Mode.
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$06
MREAD_
STAT
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
MARGIN_
RD_ACT
MARGIN_
RD_ERR
Reset Value
0
0
0
0
0
0
0
0
Table 70. Margin read status register (MREAD_STAT)
Note: The user enabled OTP margin read test is not intended for use in normal
operation. It is intended for use only after user OTP programming during manufacturing.
11.2.4.1 Margin read active status (MARGIN_RD_ACT)
The margin read active status bit is set if a user enabled OTP margin read test is in
process. The status bit is automatically cleared when the OTP margin read test is
complete. See Section 11.2.7.1 for details regarding the user enabled OTP margin read
test.
MARGIN_RD_ACT
Condition
0
No Margin Read Test is in Process
1
Margin Read Test is in Process
Table 71. Margin read active status (MARGIN_RD_ACT)
11.2.4.2 Margin read error status (MARGIN_RD_ERR)
The margin read error status bit is set if a user enabled OTP margin read test has failed.
The margin read error status bit is cleared on a read of the MREAD_STAT register. The
margin read error status bit has no impact on device operation or performance. See
Section 11.2.7.1 for details regarding the user enabled OTP margin read test.
MARGIN_RD_ERR
Condition
0
No Margin Read Test Failure
1
Margin Read Test Failure
Table 72. Margin read error status (MARGIN_RD_ERR)
FXLS9xxx0
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 6 — 8 February 2021
49 / 247



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