PIMXRT516SCVP2A datasheet(97/128 Pages) NXP

97 / 128 page

Electrical characteristics

i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021

NXP Semiconductors

4.9.4.1.4

MII serial management channel timing (ENET_MDIO and ENET_MDC)

The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3

MII specification. However the ENET can function correctly with a maximum MDC frequency of

15 MHz.

Figure 47 shows MII asynchronous input timings. Table 93 describes the timing parameters (M10–M15)

shown in the figure.

Figure 47. MII serial management channel timing diagram

4.9.4.2

RMII mode timing

In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference

clock.

Figure 48 shows RMII mode timings. Table 94 describes the timing parameters (M16–M21) shown in the

figure.

Table 93. MII serial management channel timing

Characteristic

Min.

Max.

Unit

M10

ENET_MDC falling edge to ENET_MDIO output invalid (min.

propagation delay)

0—

M11

ENET_MDC falling edge to ENET_MDIO output valid (max.

propagation delay)

—5

M12

ENET_MDIO (input) to ENET_MDC rising edge setup

—

M13

ENET_MDIO (input) to ENET_MDC rising edge hold

—

M14

ENET_MDC pulse width high

40%

60%

ENET_MDC period

M15

ENET_MDC pulse width low

40%

60%

ENET_MDC period

ENET_MDC (output)

ENET_MDIO (output)

M14

M15

M10

M11

M12

M13

ENET_MDIO (input)

PIMXRT516SCVP2A bảng dữ liệu(PDF) 97 Page - NXP Semiconductors

PIMXRT516SCVP2A bảng dữ liệu(HTML) 97 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL