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VSP2265GSJR bảng dữ liệu(PDF) 13 Page - Texas Instruments

tên linh kiện VSP2265GSJR
Giải thích chi tiết về linh kiện  CCD Signal Processor with Timing Generator for Digital Cameras
PDF  88 Pages
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nhà sản xuất  TI [Texas Instruments]
Trang chủ  http://www.ti.com
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VSP2265GSJR bảng dữ liệu(HTML) 13 Page - Texas Instruments

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Theory of Operation
9
SLES056—December 2002
VSP2265
An on-chip V-rate timing generator creates all the signals that are required for specific CCD image sensors.
The TG contains the line and pixel counters used to generate V-rate timing. Figure 2–2 is the block diagram
of the line and pixel counter circuit. A maximum 2047 lines and 4095 pixels per line are supported in time scale.
Decoder
H[10:0]
P[12:0]
RST
Line Counter
(MAX 2047 lines)
clk
VD
13 Bit
RST
Pixel Counter
(MAX 4095 Pixels)
clk
11 Bit
F/F
F/F
SYSRST
HD
MCLK
Figure 2–2. VSP2265 Line and Pixel Counter Block Diagram
Figure 2–4 shows a V-rate timing generator block diagram. By one H (horizontal line) before CCD readout,
serial data transfer must be completed by the user, and data must be loaded in the registers containing CCD
model, operation mode, integration time, and electronic zoom area information. Just before CCD readout,
information in the registers is supplied automatically to the decoder, which generates the V-rate signal using
line counter and pixel counter data. Not only the signals used for the CCD, but also the strobe light control
signal is supported. CPOB, CLPD, and PBLK can select either the internal generation mode or the external
supply mode.



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