ADA4255ACPZ-R7 datasheet(54/64 Pages) AD

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Data Sheet

ADA4255

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GPIO DIRECTION REGISTER (GPIO_DIR)

DETAILS

Table 22. GPIO_DIR Register Details (Register 0x08)

Bit 7

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit Name

Reserved

GPIO_DIR[6:0]

Access

Reserved

R/W

Reset

Reserved

Bits[6:0], GPIO_DIR—GPIO Direction

Configuration

The GPIO_DIR bit field is used to configure each GPIOx pin as

either an input or an output. Setting a bit in this bit field to 1

configures the corresponding GPIOx pin as an output. Clearing a bit

in this bit field to 0 configures the corresponding GPIOx as an input.

SEQUENTIAL CHIP SELECT REGISTER (SCS)

DETAILS

Table 23. SCS Register Details (Register 0x09)

Bit 7

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit Name

Reserved

SCS[6:0]

Access

Reserved

R/W

Reset

Reserved

Bits[6:0], SCS—Sequential Chip Select

Configuration

Bits[6:0] configure the GPIOx pins as sequential chip select (SCS)

pins. Setting any bit in SCS6 to SCS0 to 1 and configuring the

respective GPIOx pin as an output via the GPIO_DIR register

makes that GPIOx function as a chip select pin for a slave device.

When SCS is used, the first CS pulse addresses the first GPIOx

configured for SCS. Subsequent CS pulses address the remainder

of the GPIOx pins configured for SCS, and the last CS pulse

addresses the ADA4255. This sequence repeats in a round robin

format until the ADA4255 is configured otherwise. This process is

shown in Figure 112.

Slave SCS lines may require pull-up resistors to avoid inadvertently

communicating with slave devices during SCS configuration.

Figure 112. Sequential Chip Select Flowchart

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