Micrel, Inc.

MICRF620

December 2005

10

M9999-120205

Programming Interface Timing

Figure 4 and Table 6 show the timing specification for the 3-wire serial programming interface.

CS

SCLK

IO

A6

A5

A0

RW

D7

D6

D2

D1

D0

Address Register

Data Register

LOAD

Tscl

Twrite

Tread

Thigh

Tlow

Tper

Tcsr

traise

tfall

Figure 4. Programming Interface Timing

Values

Symbol

Parameter

Min.

Typ.

Max.

Units

Tper

Min. period of SCLK (Voltage dividers on IO lines will slow down the

write/read frequency)

50

ns

Thigh

Min. high time of SCLK

20

ns

Tlow

Min. low time of SCLK

20

ns

tfall

Max. time of falling edge of SCLK

1

µs

trise

Max. time of rising edge of SCLK

1

µs

Tcsr

Max. time of rising edge of CS to falling edge of SCLK

0

ns

Tcsf

Min. delay from rising edge of CS to rising edge of SCLK

5

ns

Twrite

Min. delay from valid IO to falling edge of SCLK during a write operation

0

ns

Tread

Min. delay from rising edge of SCLK to valid IO during a read operation

(assuming load capacitance of IO is 25pF)

75

ns

Time from power up to first rising edge of CS

(Assuming Vdd rail rise time of 100

µsec)

3.4

ms

Table 6. Timing Specification for the 3-wire Programming Interface