PIMXRT516SCVJ2A datasheet(36/128 Pages) NXP

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i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021

NXP Semiconductors

Electrical characteristics

4.2

System power and clocks

This section provides the information about the system power and clocks.

4.2.1

Power supplies requirements and restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state

guidelines as described in this section to guarantee the reliable operation of the device. Any deviation

from these sequences may result in the following situations:

•

Excessive current during power-up phase

•

Prevention of the device from booting

•

Irreversible damage to the processor (worst-case scenario)

Figure 4 shows the power sequence.

Figure 4. Power sequence

4.2.1.1

Power-up sequence

The below restrictions must be followed:

•

VDD_SNVS_IN supply must be turned on before any other power supply or be connected

(shorted) with VDD_LPSR_IN and DCDC_IN supply.

•

If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other

supply is switched on.

•

When internal DCDC is enabled, external delay circuit is required to delay the

“DCDC_PSWITCH” signal at least 1 ms after DCDC_IN is stable.

VDD_SNVS_IN

VDD_SNVS_ANA

VDD_SNVS_DIG

VDD_LPSR_IN

VDD_LPSR_ANA

VDD_LPSR_DIG

DCDC_IN

VDDA_1P8

VDD_SOC_IN

1ms

DCDC_PSWITCH

POR_B

ONOFF

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