ACE25QC200GLTMTH datasheet(28/64 Pages) ACE

28 / 64 page

ACE25QC200GL

2M BIT SPI NOR FLASH

VER 1.1

Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode

The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing

a “Set Burst with Wrap” (77h) instruction prior to EBh. The “Set Burst with Wrap” (77h) instruction can either

enable or disable the “Wrap Around” feature for the following EBh instructions. When “Wrap Around” is

enabled, the data being accessed can be limited to an 8, 16, 32 or 64-byte section of a 256-byte page. The

output data starts at the initial address specified in the instruction, once it reaches the ending boundary of

the 8/16/32/64- byte section, the output will wrap around to the beginning boundary automatically until /CS

is pulled high to terminate the instruction.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then

fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read

instructions.

The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable

or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around

section within a page. Refer to Set Burst with Wrap (77h) for detail descriptions.

Figure14. Fast Read Quad I/O Instruction (Initial instruction or previous M5-

4≠10)

Figure15. Fast Read Quad I/O Instruction (Previous instruction set M5-4 = 10 )

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