ACE25QC200GLFMLTH datasheet(5/64 Pages) ACE

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ACE25QC200GL

2M BIT SPI NOR FLASH

VER 1.1

Serial Input (SI)/IO0

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and

data to be programmed. Values are latched on the rising edge of serial SCK clock signal.

SI becomes IO0 an input and output during Dual and Quad SPI mode for receiving instructions, addresses,

and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out

data (on the falling edge of SCK).

Serial Data Output (SO)/IO1

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of

the serial SCK clock signal.

SO becomes IO1 an input and output during Dual and Quad SPI mode for receiving instructions, addresses,

and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out

data (on the falling edge of SCK).

Write Protect (/WP)/IO2

When /WP is driven Low (VIL), while the Status Register Protect bits (SRP1 and SRP0) of the Status

Registers (SR2[0] and SR1[7]) are set to 0 and 1 respectively, it is not possible to write to the Status

Registers. This prevents any alteration of the Status Registers. As a consequence, all the data bytes in the

memory area that are protected by the Block Protect, BP4, BP3 bits in the status registers, are also

hardware protected against data modification while /WP remains Low. The /WP function is not available

when the Quad mode is enabled (QE) in Status Register 2 (SR2[1]=1).

The /WP function is replaced by IO2 for input and output during Quad mode for receiving addresses, and

data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data

(on the falling edge of SCK). /WP has an internal pull-up resistance; when unconnected; /WP is at VIH and

may be left unconnected in the host system if not used for Quad mode.

HOLD (/HOLD)/IO3

The /HOLD signal goes low to stop any serial communications with the device, but doesn’t stop the

operation of write status register, programming, or erasing in progress.

The operation of HOLD, need /CS keep low, and starts on falling edge of the /HOLD signal, with SCLK

signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD

condition ends on rising edge of /HOLD signal with SCLK being low (If SCLK is not being low, HOLD

operation will not end until SCLK being low).

When QE=0, the IO3 pin can be configured either as a /HOLD pin. When QE=1, the /HOLD function is not

available.

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