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PIMXRT516SCVM5A bảng dữ liệu(PDF) 34 Page - NXP Semiconductors |
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PIMXRT516SCVM5A bảng dữ liệu(HTML) 34 Page - NXP Semiconductors |
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34 / 124 page ![]() i.MX RT1160 Crossover Processors Data Sheet for Extended Industrial Products, Rev. 0, 04/2021 34 NXP Semiconductors Electrical characteristics NOTE The voltage on DCDC_PSWITCH pin should be below 0.5 V before ramping up the voltage on DCDC_PSWITCH. NOTE The power rail VDD_SNVS_DIG is controlled by software. NOTE Need to ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 V supply (for example, from the external components that use both the 1.8 V and 3.3 V supplies). NOTE USB1_VBUS, USB2_VBUS, and VDDA_ADC_3P3 are not part of the power supply sequence and may be powered at any time. 4.2.1.2 Power-down sequence The following restrictions must be followed: • VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_LPSR_IN and DCDC_IN supply. • If a coin cell is used to power VDD_SNVS_IN, then ensure that it is removed after any other supply is switched off. 4.2.1.3 Power supplies usage I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_XXXX) is OFF. This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O power supply of each pin, see “Power Rail” columns in pin list tables of Section 6, Package information and contact assignments.” 4.2.2 Internal POR and power detect Internal detector monitors VDD_SOC_IN and VDD_LPSR_DIG. Internal POR will be asserted whenever VDD_SOC_IN or VDD_LPSR_DIG are lower than the valid voltage values shown in the Table 15. Table 15. Internal POR and power detect Symbol Description Value Unit Vdetlpsr1p0_H 1.0 V supply valid 0.75 V Vdetsoc1p0_H 1.0 V supply valid 0.75 V Hystdet1p0 The detector hysteresis 100 mV |
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