DM7495N datasheet(3/6 Pages) NSC

3 / 6 page

Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load)

Symbol

Parameter

From (Input)

RL e 400X CL e 15 pF

Units

To (Output)

Min

Max

fMAX

Maximum Clock Frequency

MHz

tPHL

Propagation Delay Time

Clock to

High to Low Level Output

Output

tPLH

Propagation Delay Time

Clock to

Low to High Level Output

Output

Function Table

Inputs

Outputs

Mode

Clocks

Serial

Parallel

Control

2(L)

1(R)

QA0

QB0

QC0

QD0

XXa

dQBn

QCn

QDn

QA0

QB0

QC0

QD0

QAn

QBn

QCn

QAn

QBn

QCn

QA0

QB0

QC0

QD0

QA0

QB0

QC0

QD0

QA0

QB0

QC0

QD0

QA0

QB0

QC0

QD0

QA0

QB0

QC0

QD0

Shifting left requires external connection of QB to A QC to B QD to C Serial data is entered at input D

H e High Level (Steady State) L e Low Level (Steady State) X e Don’t Care (Any input including transitions)

v e Transition from high to low level u e Transition from low to high level

a b c d e The level of steady state input at inputs A B C or D respectively

QA0 QB0 QC0 QD0 e The level of QA QB QC QD respectively before the indicated steady state input conditions were established

QAn QBn QCn QDn e The level of QA QB QC QD respectively before the most recent

v transition of the clock

Logic Diagram

TLF6534 – 2

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