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ACE24AC512EDPTH bảng dữ liệu(PDF) 9 Page - ACE Technology Co., LTD. |
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ACE24AC512EDPTH bảng dữ liệu(HTML) 9 Page - ACE Technology Co., LTD. |
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9 / 18 page ![]() ACE24AC512E Two-wire Serial EEPROM VER 1.1 9 Figure 7: Random Read Figure 8: SCL and SDA Bus Timing Electrical Specifications A. Power-Up Requirements During a power-up sequence, the VCC supplied to the device should monotonically rise from GND to the minimum VCC level, with a slew rate no faster than 0.05 V/μs and no slower then 0.1 V/ms. A decoupling cap should be connected to the VCC PAD which is no smaller than 10nF. B. Device Reset To prevent inadvertent write operations or any other spurious events from occurring during a power- up sequence, this device includes a Power-on Reset (POR) circuit. Upon power-up, the device will not respond to any commands until the VCC level crosses the internal voltage threshold (VPOR) that brings the device out of Reset and into Standby mode. The system designer must ensure the instructions are not sent to the device until the VCC supply has reached a stable value greater than or equal to the minimum VCC level. |
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