PIMXRT516SCVP5A datasheet(90/124 Pages) NXP

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i.MX RT1160 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 04/2021

NXP Semiconductors

Electrical characteristics

Figure 42 depicts the timing of HS400.

Figure 43. HS400 timing

4.9.3.6

Bus operation condition for 3.3 V and 1.8 V signaling

Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of

SDR104/SDR50/HS200/HS400 mode is 1.8 V.

4.9.4

Ethernet controller (ENET) AC electrical specifications

4.9.4.1

ENET MII mode timing

This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal

timings.

4.9.4.1.1

MII receive signal timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER, and ENET_RX_CLK)

The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There

is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the

ENET_RX_CLK frequency.

SD7

SD1

SD5

SD6

SCK

Output from

Strobe

Input from

uSDHC to eMMC

eMMC to uSDHC

DAT0

DAT1

DAT7

...

DAT0

DAT1

DAT7

...

SD4

SD3

SD2

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