MCP3565R datasheet(63/108 Pages) MICROCHIP

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2020-2021 Microchip Technology Inc.

DS20006401C-page 63

MCP3565R

6.0

SPI SERIAL INTERFACE AND

DEVICE OPERATION

6.1

Overview

The MCP3565R device uses an SPI interface to read

and write the internal registers. The device includes a

four-wire (CS, SCK, SDI, SDO) serial SPI interface that

is compatible with SPI Modes 0,0 and 1,1. Data are

clocked out of the device on the falling edge of SCK

and data are clocked into the device on the rising edge

of SCK. In these modes, the SCK clock can Idle either

high (1,1) or low (0,0). The digital interface is asynchro-

nous with the ADC conversion clock (i.e., the MLCK

clock controls the ADC sampling and digital filtering

when the internal oscillator is selected as the conver-

sion clock source). However, when an external clock is

selected as the conversion clock source, SCK

becomes MCLK; therefore, it makes the interface and

conversion clock synchronous signals. All digital input

pins are Schmitt Triggered to avoid system noise

perturbations on the communications. The SPI inter-

face is maintained in a Reset state during POR.

Each SPI communication starts with a CS falling edge

and stops with the CS rising edge. Each SPI communi-

cation is independent. When CS is logic high, SDO is

in high-impedance, the transitions on SCK and SDI

have no effect. Changing from SPI Mode 1,1 to an SPI

Mode 0,0 and vice versa is possible, and must be done

while the CS pin is logic high. Any CS rising edge clears

the communication and resets the SPI digital interface.

See Figure 1-1 for the SPI timing details.

The MCP3565R digital interface is capable of handling

various Continuous Read and Write modes, which

allows for ADC data streaming, or full register map

writing, within only one communication (and with only

one unique COMMAND byte). It also includes single

byte Fast commands. The device does not include a

Master Reset pin, but it includes an SPI Fast command

to be able to fully reset the part at any time and place it

back in a default configuration.

The device family also includes advanced security

features to secure communication and alert users of

unwanted Write commands that change the desired

configuration. To secure the entire configuration, the

device includes an 8-bit lock code (LOCK[7:0]), which

blocks all Write commands to the full register map if the

value of the lock code is not equal to a defined

password (0xA5). The user can protect its configuration

by changing the LOCK[7:0] value to 0x00 after full

programming, so that any unwanted Write command

will not result in a change in the configuration. Each SPI

read communication can be secured through a select-

able CRC-16 checksum provided on the SDO pin at the

end of every communication sequence. This checksum

computation is compatible with the DMA CRC

hardware of the PIC24 and PIC32 MCUs, as well as

many other MCU references, resulting in no additional

overhead for the added security.

Once the part is locked (write-protected), an additional

checksum calculation also runs continuously in the

background to ensure the integrity of the full register

map. All writable registers of the register map are

processed through a CRC-16 calculation engine and

give a CRC-16 checksum that depends on the con-

figuration. This checksum is readable from the CRC

a change in the checksum, a CRC interrupt generates

a flag to warn the user that the configuration has been

corrupted.

The MCP3565R device does not incorporate a

dedicated IRQ pin, but two IRQ mechanisms are avail-

able for users to synchronize with Data Ready Events,

and retrieve POR and CRC errors that could happen

during operations. MCP3565R does not incorporate a

dedicated MCLK I/O pin, as the rest of the family of

MCP356x devices, due to its low pin count. However,

the SCK pin can be used as an input to retrieve MCLK

from an external clock source, or as an output to gather

AMCLK generated by the internal oscillator to

synchronize with the MCU.

6.2

SPI Communication Structure

The MCP3565R interface has a simple communication

structure. Every communication starts with a CS falling

edge and stops with a CS rising edge.

The communication is always started by the

COMMAND byte (8 bits) clocking on the SDI input. The

COMMAND byte defines the command that will be

executed by the digital interface. It includes the device

address, the register address bits and the

command-type bits.

The COMMAND byte is typically followed by data bytes

clocked on SDI if the command type is a write and on

SDO if the command type is a read. The COMMAND

byte can also define a Fast command, and in this case,

it is not followed by any other byte. The following sub-

sections detail the COMMAND byte structure and all

possible commands.

During the COMMAND byte clocking on SDI, a

STATUS byte is also propagated on the SDO output to

enable easy polling of the device status. During this time,

the interface is full-duplex, but the part can still be used

by MCUs handling only half-duplex communications if

the STATUS byte is ignored.

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