PIMXRT516SCVL2A datasheet(63/124 Pages) NXP

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Electrical characteristics

i.MX RT1160 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 04/2021

NXP Semiconductors

Figure 24. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2)

4.5.2.2

FlexSPI output/write timing

The following sections describe output signal timing for the FlexSPI controller including control signals

and data outputs.

4.5.2.2.1

SDR mode

NOTE

TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register, the

default values are shown above. Please refer to the i.MXRT1160 Reference

Manual (IMXRT1160RM) for more details.

Table 57. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2)

Symbol

Parameter

Min

Max

Unit

Frequency of operation

—

166

MHz

TSCKD - TSCKDQS

Time delta between TSCKD and TSCKDQS

-1

Table 58. FlexSPI output timing in SDR mode

Symbol

Parameter

Min

Max

Unit

Frequency of operation

—

1661

1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing

specifications.

MHz

Tck

SCK clock period

6.0

—

TDVO

Output data valid time

—

TDHO

Output data hold time

—

TCSS

Chip select output setup time

3 x TCK - 1

—

TCSH

Chip select output hold time

3 x TCK + 2

—

TSCKD

TSCK2DQS

SCK2

SIO[0:7]

DQS

SCK

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