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MCP37D11T-80E/TE bảng dữ liệu(PDF) 33 Page - Microchip Technology |
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MCP37D11T-80E/TE bảng dữ liệu(HTML) 33 Page - Microchip Technology |
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33 / 136 page ![]() 2020 Microchip Technology Inc. DS20006381A-page 33 MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC TABLE 4-1: EXAMPLE: CHANNEL ORDER SELECTION USING ADDRESSES 0X7D – 0X7F No. of Channels(1) Selected Channels Channel Order(2) Address 0x7F Address 0x7E Address 0x7D b 7 b 0 b 7 b 0 b 7 b 0 8 Channel Order Bit Settings 5th Ch. 4th Ch. 6th Ch. 3rd Ch. 7th Ch. 2nd Ch. 8th Ch. 1st Ch. [0 1 2 3 4 5 6 7] [0 1 2 3 4 5 6 7] (Default) 1 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 0 [7 6 5 4 3 2 1 0] [7 6 5 4 3 2 1 0] 0 1 1 1 0 0 0 1 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1 [0 2 4 6 1 3 5 7] [0 2 4 6 1 3 5 7] 0 0 1 1 1 0 0 1 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 0 [1 3 5 7 0 2 4 6] [1 3 5 7 0 2 4 6] 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 0 1 7 Channel Order Bit Settings Unused 4th Ch. 5th Ch. 3rd Ch. 6th Ch. 2nd Ch. 7th Ch. 1st Ch. [0 1 2 3 4 5 6] [0 1 2 3 4 5 6 7] 111 0 1 1 1 0 0 0 1 0 1 0 1 0 0 1 1 1 0 0 0 0 [0 2 4 6 1 3 5] [0 2 4 6 1 3 5 7] 111 1 1 0 0 0 1 1 0 0 0 1 1 0 1 0 1 0 1 0 0 0 6 Channel Order Bit Settings Unused Unused 4th Ch. 3rd Ch. 5th Ch. 2nd Ch. 6th Ch. 1st Ch. [0 1 2 3 4 5] [0 1 2 3 4 5 6 7] 111110 0 1 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 [0 2 4 6 1 3] [0 2 4 6 1 3 5 7] 111101 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 5 Channel Order Bit Settings Unused Unused Unused 3rd Ch. 4th Ch. 2nd Ch. 5th Ch. 1st Ch. [0 1 2 3 4] [0 1 2 3 4 5 6 7] 110101 111 0 1 0 0 1 1 0 0 1 1 0 0 0 0 0 [0 2 4 6 1] [0 2 4 6 1 3 5 7] 101011 111 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 4 Channel Order Bit Settings Unused Unused Unused Unused 3rd Ch. 2nd Ch. 4th Ch. 1st Ch. [0 1 2 3] [0 1 2 3 4 5 6 7] 110101 111100 0 1 0 0 0 1 0 1 1 0 0 0 [4 5 6 7] [4 5 6 7 0 1 2 3] 010001 011000 1 1 0 1 0 1 1 1 1 1 0 0 [0 2 4 6] [0 2 4 6 1 3 5 7] 101011 111001 1 0 0 0 1 0 1 1 0 0 0 0 [1 3 5 7] [1 3 5 7 0 2 4 6] 100010 110000 1 0 1 0 1 1 1 1 1 0 0 1 3 Channel Order Bit Settings Unused Unused Unused Unused Unused 2nd Ch. 3rd Ch. 1st Ch. [0 1 2] [0 1 2 3 4 5 6 7] 101100 11001111 1 0 0 1 0 1 0 0 0 0 [0 2 4] [0 2 4 6 1 3 5 7] 011001 10111011 1 0 1 0 1 0 0 0 0 0 2 Channel Order Bit Settings Unused Unused Unused Unused Unused Unused 2nd Ch. 1st Ch. [0 1] [0 1 2 3 4 5 6 7] 101100 11001111 1010 0 0 1 0 0 0 [2 3] [2 3 0 1 4 5 6 7] 101100 11000111 1000 0 1 1 0 1 0 [4 5] [4 5 0 1 2 3 6 7] 011010 11000110 1000 1 0 1 1 0 0 [6 7] [6 7 0 1 2 3 4 5] 011010 10000110 1000 1 1 1 1 1 0 Note 1: Defined by SEL_NCH<2:0> in Address 0x01 (Register 5-2). 2: Individual channel order should not be repeated. Unused channels are still assigned after the selected channel address. The order of the unused channel addresses has no meaning since they are not used. |
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