IMXRT1010CEC datasheet(39/65 Pages) NXP

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Electrical characteristics

i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019

NXP Semiconductors

Figure 20. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B2)

4.5.1.2

FlexSPI output/write timing

The following sections describe output signal timing for the FlexSPI controller including control signals

and data outputs.

4.5.1.2.1

SDR mode

NOTE

CSS and TCSH are configured by the FlexSPIn_FLSHAxCR1

RT1010 Reference Manual (IMXRT1010RM) for more details.

Figure 21. FlexSPI output timing in SDR mode

Table 35. FlexSPI output timing in SDR mode

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation

—

1331

The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing

specifications.

MHz

Tck

SCK clock period

6.0

—

TDVO

Output data valid time

—

TDHO

Output data hold time

-1

—

TCSS

Chip select output setup time

3 x TCK -1

—

TCSH

Chip select output hold time

3 x TCK + 2

—

TSCKD

TSCK2DQS

SCK2

SIO[0:7]

DQS

SCK

T CSS

T CK

TCSH

TDVO

TDHO

TDVO

TDHO

SCK

SIO[0:7]

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