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CY24239
Document #: 38-07038 Rev. **
Page 8 of 15
Note:
2.
CPU and PCI frequency selections are listed in Table 2 and Table 6.
Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
Spread Spectrum
Data Byte 0, Bit 3 = 1
CPU, SDRAM
Clocks (MHz)
PCI Clocks
(MHz)
Percentage
Bit 2
SEL_3
Bit 6
SEL_2
Bit 5
SEL_1
Bit 4
SEL_0
1111
91.66
30.5
OFF
1110
75.0
25.0
OFF
1101
100.0
33.3
OFF
1100
83.3
27.76
OFF
1011
66.6
33.3
OFF
1010
105.0
26.3
OFF
1001
110.0
27.5
OFF
1000
133.3
33.3
OFF
0111
91.66
30.5
–1.2%
0110
75.0
25.0
–1.2%
0101
100.0
33.3
–1.2%
0100
83.3
27.76
–1.2%
0011
91.66
30.5
–2.4%
0010
75.0
25.0
–2.4%
0001
100.0
33.3
–2.4%
0000
83.3
27.76
–2.4%
Table 7. Select Function for Data Byte 0, Bits 0
Function
Input Conditions
Output Conditions
Data Byte 0
CPU_F, 1:2
PCI_F,
PCI0:5
REF0:1,
IOAPIC0,_F
48MHZ
24MHZ
Bit 0
Normal Operation
0
Note 2
Note 2
14.318 MHz
48 MHz
24 MHz
Three-state
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
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