ADRF6821 datasheet(49/61 Pages) AD

49 / 61 page

Data Sheet

ADRF6821

Rev. A | Page 49 of 61

Address: 0x1205, Reset: 0x00, Name: SD_PHASE_L_0

Sigm a-Delta Phas e Word

[7:0] PHASE[7:0] (R/W)

Table 53. Bit Descriptions for SD_PHASE_L_0

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

PHASE,

Bits[7:0]

Sigma-Delta Phase Word. If phase adjust mode is enabled (PHASE_ADJ_EN = 1), the

phase in the DSM is incremented by this amount on each phase adjustment trigger.

The phase adjustment trigger can be caused by the SPI via a write to the LSB of this

represented as an unsigned 24-bit fractional number, in units of VCO cycles. It,

therefore, has a resolution of 21 µ°. For example, to adjust the phase by 5° of the

fundamental VCO, program this word to (5°/360°) × 224 = 233,017. This process can

be done repetitively to effectively recede by multiple VCO cycles or to embed the

PLL itself inside the phase or frequency control loops under some other supervisory

control. The phase adjust feature cannot be done any faster than once every five PFD

cycles and by no more than 180° on any individual adjustment.

0x0

R/W

Address: 0x1206, Reset: 0x00, Name: SD_PHASE_M_0

Sigm a-Delta Phas e Word

[7:0] PHASE[15:8] (R/W )

Table 54. Bit Descriptions for SD_PHASE_M_0

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

PHASE,

Bits[15:8]

Sigma-Delta Phase Word. If phase adjust mode is enabled (PHASE_ADJ_EN = 1), the

phase in the DSM is incremented by this amount on each phase adjustment trigger.

The phase adjustment trigger can be caused by the SPI via a write to the LSB of this

represented as an unsigned 24-bit fractional number, in units of VCO cycles. It,

therefore, has a resolution of 21 µ°. For example, to adjust the phase by 5° of the

fundamental VCO, program this word to (5°/360°) × 224 = 233,017. This process can be

done repetitively to effectively recede by multiple VCO cycles or to embed the PLL

itself inside the phase or frequency control loops under some other supervisory

control. The phase adjust feature cannot be done any faster than once every five PFD

cycles and by no more than 180° on any individual adjustment.

0x0

R/W

Address: 0x1207, Reset: 0x00, Name: SD_PHASE_H_0

Sigm a-Delta Phas e Word

[7:0] PHASE[23:16] (R/W)

Table 55. Bit Descriptions for SD_PHASE_H_0

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

PHASE,

Bits[23:16]