ADRF6806ACPZ-R7 datasheet(19/36 Pages) AD

tên linh kiện	ADRF6806ACPZ-R7

Giải thích chi tiết về linh kiện	50 MHz to 525 MHz Quadrature Demodulator with Fractional-N PLL and VCO

PDF	36 Pages

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19 / 36 page

Data Sheet

ADRF6806

Rev. B | Page 19 of 36

With R5[DB5] = 1, the ADRF6806 is in a lower power operating

mode. The device is still fully functional in this lower power

mode, but the mixer performance is shifted (see the Typical

Performance Characteristics section for details on performance

differences). Setting R5[DB5] = 0 causes the ADRF6806 mixer

stage to run at a higher current, thereby achieving a higher IIP3.

an input or output and whether the output driver is enabled as

detailed in Figure 38.

DEMOD

BIAS

ENABLE

LOW

POWER

MODE

ENABLE

IN/OUT

CTRL

OUTPUT

DRIVER

ENABLE

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8

DB7

DMBE

DB6

DB5

DB4

DB3

DB2 DB1 DB0

LPEN

LXL

LDRV C3(1) C2(0) C1(1)

LDRV

LXL

LPEN

DISABLED

ENABLED (DEFAULT)

LO OUTPUT DRIVER

ENABLE

DRIVER OFF (DEFAULT)

DRIVER ON

DMBE

DISABLE

ENABLE (DEFAULT)

DEMOD BIAS ENABLE

LO IN/OUT CONTROL

LO OUTPUT (DEFAULT)

LO INPUT

LOW POWER MODE

CONTROL BITS

000

Figure 38. LO Path and Demodulator Control Register (R5)

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