ADRF6755ACPZ datasheet(21/48 Pages) AD

21 / 48 page

Data Sheet

ADRF6755

Rev. B | Page 21 of 48

THEORY OF OPERATION

OVERVIEW

The ADRF6755 device can be divided into the following basic

building blocks:

•

PLL synthesizer and VCO

•

Quadrature modulator

•

Attenuator

•

Voltage regulator

•

I2C/SPI interface

Each of these building blocks is described in detail in the

sections that follow.

PLL SYNTHESIZER AND VCO

Overview

The phase-locked loop (PLL) consists of a fractional-N frequency

synthesizer with a 25-bit fixed modulus, allowing a frequency

resolution of less than 1 Hz over the entire frequency range. It

also has an integrated voltage-controlled oscillator (VCO) with

a fundamental output frequency ranging from 2310 MHz to

4800 MHz. An RF divider, controlled by Register CR28,

Bits[2:0], extends the lower limit of the local oscillator (LO)

frequency range to 100 MHz. See Table 6 for more details on

Reference Input Section

The reference input stage is shown Figure 52. SW1 and SW2 are

normally closed switches. SW3 is normally open. When power-

down is initiated, SW3 is closed, and SW1 and SW2 are open. This

ensures that there is no loading of the REFIN pin at power-down.

Figure 52. Reference Input Stage

Reference Input Path

The on-chip reference frequency doubler allows the input

reference signal to be doubled. This is useful for increasing the

PFD comparison frequency. Making the PFD frequency higher

improves the noise performance of the system. Doubling the

PFD frequency usually improves the in-band phase noise

performance by up to 3 dBc/Hz.

The 5-bit R-divider allows the input reference frequency (REFIN) to

be divided down to produce the reference clock to the PFD.

Division ratios from 1 to 32 are allowed.

An additional divide-by-2 (÷2) function in the reference input

path allows for a greater division range.

Figure 53. Reference Input Path

The PFD frequency equation is

fPFD = fREFIN × [(1 + D)/(R × (1 + T))]

(1)

where:

fREFIN is the reference input frequency.

D is the doubler bit.

R is the programmed divide ratio of the binary 5-bit

programmable reference divider (1 to 32).

T is the R/2 divider setting bit (CR10[6] = 0 or 1).

If no division is required, it is recommended that the 5-bit

R-divider and the divide-by-2 be disabled by setting CR5[4] = 0.

If an even numbered division is required, enable the divide-by-2

by setting CR5[4] = 1 and CR10[6] = 1 and implement the

remainder of the division in the 5-bit R-divider. If an odd number

division is required, set CR5[4] = 1 and implement all of the

division in the 5-bit R-divider.

RF Fractional-N Divider

The RF fractional-N divider allows a division ratio in the PLL

feedback path that can range from 23 to 4095. The relationship

between the fractional-N divider and the LO frequency is

described in the INT and FRAC Relationship section.

INT and FRAC Relationship

The integer (INT) and fractional (FRAC) values make it possible to

generate output frequencies that are spaced by fractions of the

phase frequency detector (PFD) frequency. See the Example—

Changing the LO Frequency section for more information.

The LO frequency equation is

LO = fPFD × (INT + (FRAC/225))/2RFDIV

(2)

where:

LO is the local oscillator frequency.

fPFD is the PFD frequency.

INT is the integer component of the required division factor

and is controlled by the CR6 and CR7 registers.

FRAC is the fractional component of the required division

factor and is controlled by the CR0 to CR3 registers.

RFDIV is set in Register CR28, Bits[2:0], and controls the

setting of the divider at the output of the PLL.

Figure 54. RF Fractional-N Divider

BUFFER

R-DIVIDER

REFIN

100

kΩ

SW2

SW3

SW1

POWER-DOWN

CONTROL

×2

DOUBLER

5-BIT

R-DIVIDER

FROM

REFIN

PFD

÷2

N-COUNTER

INT

REG

PFD

RF N-DIVIDER

N = INT + FRAC/225

FROM VCO

OUTPUT

DIVIDERS

FRAC

VALUE

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

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